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kv5x data sheet 240 mhz cortex-m7 based mcu for real-time, high performance connected control the kinetis kv5x family of mcu is a high-performance solution offering exceptional precision, sensing, and control targeting motor control, industrial drives and automation, and power conversion. apart from the high performance cortex-m7 core, it features top notch real time control peripherals such as high resolution pulse-width modulation (pwm) with 260 ps resolution, 4 fast 12-bit adcs with 5 msps, up to 44 pwm channels for supporting multi-motor systems. it also comes with multiple communication peripherals including 3 flexcan modules, optional ethernet communications, and multiple uart, spi, and i2c modules. the kv5x is supported by a comprehensive enablement suite from nxp and third-party resources including reference designs, software libraries, and motor configuration tools. core ? arm ? cortex ? -m7 core up to 240 mhz with single precision floating point unit (fpu) memories ? up to 1 mb program flash memory ? up to 256 kb ram ? external memory interface (flexbus) system peripherals ? 32-channel dma controller ? low-leakage wakeup unit ? swd debug interface ? advanced independent clocked watchdog ? jtag debug interface clocks ? 32 to 40 khz or 3 to 32 mhz crystal oscillator ? mcg with fll and pll referencing internal or external reference clock operating characteristics ? voltage range: 1.71 to 3.6 v ? temperature range: C40 to 105 c human-machine interface ? general-purpose input/output communication interfaces ? six uart/flexsci modules with programmable 8- or 9-bit data format ? three 16-bit spi modules ? two i2c modules ? three flexcan modules ? ethernet module (optional) analog modules ? four 12-bit sar high speed adcs with 5 msps sample rate ? one 16-bit adc ? four cmps with a 6-bit dac and programmable reference input ? one 12-bit dac timers ? two eflexpwm with 4 sub-modules, with 12 pwm outputs, one eflexpwm module with less than 285 ps resolution provided by nano-edge module. ? two 8-channel flextimers (ftm0 and ftm3) ? two 2-channel flextimers (ftm1 and ftm2) ? four periodic interrupt timers (pit) ? two programmable delay blocks (pdb) ? quadrature encoder/decoder (enc) security and integrity modules mkv58f1m0vxx24 mkv56f1m0vxx24 mkv58f512vxx24 mkv56f512vxx24 144 lqfp 20 x 20 x 1.4 mm pitch 0.5 mm 144 bga 13 x 13 x 1.23 mm pitch 1.0 mm 100 lqfp 14 x 14 x 1.4 mm pitch 0.5 mm nxp semiconductors kv5xp144m240 data sheet: technical data rev. 4, 06/2016 nxp reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.
? hardware crc module to support fast cyclic redundancy checks ? external watchdog monitor (ewm) ? true random number generator (trng) ? memory mapped cryptographic acceleration unit (mmcau) ? advanced watchdog (wdog) timer modules orderable part numbers summary 1 nxp part number cpu frequency (mhz) ambient operating temperat ure (c) package flash/ sram ethernet can gpio mkv58f1m0vmd24 2 240 105 144 mapbga 1 mb/256 kb yes 3 111 mkv58f1m0vlq24 240 105 144 lqfp 1 mb/256 kb yes 3 111 mkv58f1m0vll24 240 105 100 lqfp 1 mb/256 kb yes 3 74 mkv56f1m0vmd24 2 240 105 144 mapbga 1 mb/256 kb no 2 111 mkv56f1m0vlq24 240 105 144 lqfp 1 mb/256 kb no 2 111 mkv56f1m0vll24 240 105 100 lqfp 1 mb/256 kb no 2 74 mkv58f512vmd24 2 240 105 144 mapbga 512 kb/128 kb yes 3 111 mkv58f512vlq24 240 105 144 lqfp 512 kb/128 kb yes 3 111 MKV58F512VLL24 240 105 100 lqfp 512 kb/128 kb yes 3 74 mkv56f512vmd24 2 240 105 144 mapbga 512 kb/128 kb no 2 111 mkv56f512vlq24 240 105 144 lqfp 512 kb/128 kb no 2 111 mkv56f512vll24 240 105 100 lqfp 512 kb/128 kb no 2 74 1. to confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search. 2. the 144-pin mapbga package for this product is not yet available. however, it is included in a package your way program for kinetis mcus. visit nxp.com/kpyw for more details. related resources type description resource selector guide the solution advisor is a web-based tool that features interactive application wizards and a dynamic product selector. solution advisor table continues on the next page... 2 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
related resources (continued) type description resource reference manual the reference manual contains a comprehensive description of the structure and function (operation) of a device. kv5xp144m240rm 1 data sheet the data sheet includes electrical characteristics and signal connections. kv5xp144m240 1 chip errata the chip mask set errata provides additional or corrective information for a particular device mask set. kinetis_v_0n86p 1 kinetis_v_1n86p 1 package drawing package dimensions are provided in package drawings. ? mapbga 144-pin: 98asa00222d 1 ? lqfp 144-pin: 98ass23177w 1 ? lqfp 100-pin: 98ass23308w 1 1. to find the associated resource, go to http://www.nxp.com and perform a search using this term. kv5x data sheet, rev. 4, 06/2016 3 nxp semiconductors
crossbar switch ( axbs x32 ) mcg edma dma mux 32 ch swj-dp arm cortex-m7 core ppb jtag & serial wire ahb to ips x2 tcm 64kb itcm 64kb dtcm nvic itm wic pit flash controller x256 flash 1m byte dspi x3 12-bit dac low-power timer dsp irc 4 mhz fpb dwt m2 m3 s2 s3 tpiu trace port ahbd etm sfpu rgpio osc hscmp x4 with 6b dac? 16 kb i$ cache controller mmcau pit flexsci x6 8 kb d$ 3 x flexcan i2c flexpwm irc 32-39khz 64b axim 32b ahbp 32b ahbs 64b tcm 32b tcm 32b tcm mpu s0 m1 pl301 10/100 enet nanoedge 5msps-adc x4 flexpwm smpu lpo flextimer 8ch + 8ch+ 2ch+2ch x2 x4 subm x4 subm xbara xbarb aoi pdb x2 enc wdog ewm flexbus crc pmc s0 64kb dtcm s1 s4 smpu s1 m0 m1 ocram0 64k ram s5 1588 tmr trng 16bit sar adc fll pll m0 s6 port split bme2 figure 1. kv5x block diagram 4 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
table of contents 1 ratings.................................................................................. 6 1.1 thermal handling ratings............................................... 6 1.2 moisture handling ratings............................................... 6 1.3 esd handling ratings..................................................... 6 1.4 voltage and current operating ratings............................ 6 2 general................................................................................. 7 2.1 ac electrical characteristics........................................... 7 2.2 nonswitching electrical specifications............................ 7 2.2.1 operating requirements.................................... 7 2.2.2 hvd, lvd, and por operating requirements.... 8 2.2.3 port voltage and current operating behaviors 9 2.2.4 power mode transition operating behaviors....... 10 2.2.5 power consumption operating behaviors........... 11 2.2.6 emc radiated emissions operating behaviors... 15 2.2.7 designing with radiated emissions in mind........ 16 2.2.8 capacitance attributes....................................... 16 2.3 switching specifications................................................. 16 2.3.1 typical device clock specifications.................... 16 2.3.2 general switching specifications........................ 17 2.4 thermal specifications................................................... 18 2.4.1 thermal operating requirements........................ 18 2.4.2 thermal attributes.............................................. 19 3 peripheral operating requirements and behaviors................ 19 3.1 core modules................................................................ 19 3.1.1 swd electricals ................................................ 19 3.1.2 debug trace timing specifications...................... 21 3.1.3 jtag electricals................................................. 22 3.2 system modules............................................................ 25 3.3 clock modules............................................................... 25 3.3.1 mcg specifications............................................ 25 3.3.2 oscillator electrical specifications...................... 27 3.4 memories and memory interfaces................................. 29 3.4.1 flash (ftfe) electrical specifications................ 29 3.5 flexbus switching specifications.................................... 31 3.6 security and integrity modules....................................... 34 3.7 analog............................................................................ 34 3.7.1 12-bit sar high speed analog-to-digital converter (hsadc) parameters........................ 35 3.7.2 adc electrical specifications.............................. 37 3.7.3 cmp and 6-bit dac electrical specifications...... 42 3.7.4 12-bit dac electrical characteristics.................. 43 3.8 timers............................................................................ 46 3.8.1 enhanced nanoedge pwm characteristics....... 46 3.9 communication interfaces............................................. 47 3.9.1 can switching specifications............................. 47 3.9.2 ethernet switching specifications....................... 47 3.9.3 dspi switching specifications (limited voltage range)................................................................. 49 3.9.4 dspi switching specifications (full voltage range)................................................................. 50 3.9.5 i2c..................................................................... 52 3.9.6 uart................................................................. 52 4 dimensions........................................................................... 52 4.1 obtaining package dimensions...................................... 52 5 pinouts and packaging......................................................... 53 5.1 kv5x signal multiplexing and pin assignments............ 53 5.2 kv5x pinouts................................................................. 62 6 ordering parts....................................................................... 64 6.1 determining valid orderable parts.................................. 64 7 part identification................................................................... 65 7.1 description..................................................................... 65 7.2 format........................................................................... 65 7.3 fields............................................................................. 65 7.4 example......................................................................... 66 8 terminology and guidelines.................................................. 66 8.1 definition: operating requirement.................................. 66 8.2 definition: operating behavior....................................... 66 8.3 definition: attribute........................................................ 67 8.4 definition: rating........................................................... 67 8.5 result of exceeding a rating.......................................... 67 8.6 relationship between ratings and operating requirements.................................................................. 68 8.7 guidelines for ratings and operating requirements........ 68 8.8 definition: typical value................................................. 69 8.9 typical value conditions............................................... 70 9 revision history.................................................................... 70 kv5x data sheet, rev. 4, 06/2016 5 nxp semiconductors
1 ratings 1.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.3 esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human-body model -2000 +2000 v 1 v cdm electrostatic discharge voltage, charged-device model -500 +500 v 2 i lat latch-up current at ambient temperature of 105 c -100 +100 ma 3 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . 3. determined according to jedec standard jesd78, ic latch-up test . 1.4 voltage and current operating ratings ratings 6 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
symbol description min. max. unit v dd digital supply voltage C0.3 3.6 v i dd digital supply current 220 1 ma v io digital pin input voltage (except open drain pins) C0.3 vdd + 0.3 2 v i d instantaneous maximum current single pin limit (applies to all port pins) C25 25 ma v dda analog supply voltage v dd C 0.3 v dd + 0.3 v 1. all v dd /v ss pins must be utilized for this value to be valid. 2. maximum value of v io must be 3.8 v. 2 general 2.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. 80% 20% 50% v il input signal v ih fall time high low rise time midpoint1 the midpoint is v il + (v ih - v il ) / 2 figure 2. input signal measurement reference all digital i/o switching characteristics, unless otherwise specified, assume: 1. output pins ? have c l =30pf loads, ? are slew rate disabled, and ? are normal drive strength 2.2 nonswitching electrical specifications general kv5x data sheet, rev. 4, 06/2016 7 nxp semiconductors
2.2.1 operating requirements this section includes information about recommended operating conditions. note recommended v dd ramp rate is between 1 ms and 200 ms. table 1. operating requirements (v reflx =0v, v ssa =0v, v ss =0v) symbol description notes 1 min max unit v dd digital supply voltage 1.71 3.6 v v dda analog supply voltage v dd 3.6 v v refhx adc reference voltage high 1.8 v dda v vdd voltage difference v dd to v dda -0.1 0.1 v vss voltage difference v ss to v ssa -0.1 0.1 v f_mcgou t device clock frequency ? using internal rc oscillator ? using external clock source 0.04 0 100 240 mhz v ih input voltage high (digital inputs) 0.7 x v dd v v il input voltage low (digital inputs) 0.35 x v dd v t a ambient operating temperature -40 105 c 1. default mode ? pin group 1: gpio, tdi, tdo, tms, tck ? pin group 2: reset ? pin group 3: adc and comparator analog inputs ? pin group 4: xtal, extal ? pin group 5: dac analog output ? pin group 6: ptb0, ptb1, ptd4, ptd5, ptd6, ptd7, ptc3, and ptc4. have high output current capability 2.2.2 hvd, lvd, and por operating requirements table 2. v dd supply hvd, lvd and por operating requirements symbol description min. typ. max. unit notes v por falling v dd por detect voltage 0.8 1.1 1.5 v v lvdh falling low-voltage detect threshold high range (lvdv=01) 2.48 2.56 2.64 v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 80 mv table continues on the next page... general 8 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
table 2. v dd supply hvd, lvd and por operating requirements (continued) symbol description min. typ. max. unit notes v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v v hvdh high voltage detect (high trip point) 3.7202 v v hvdl high voltage detect (low trip point) 3.4582 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 60 mv v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 s 1. rising thresholds are falling threshold + hysteresis voltage 2.2.3 port voltage and current operating behaviors table 3. voltage and current operating behaviors symbol description min. typ. max. unit notes v oh output high voltage normal drive pad except reset_b 2.7 v v dd 3.6 v, i oh = -10 ma v dd C 0.5 v 1 1.71 v v dd 2.7 v, i oh = -5 ma v dd C 0.5 v v oh output high voltage high drive pad except reset_b 2.7 v v dd 3.6 v, i oh = -20 ma v dd C 0.5 v 1 1.71 v v dd 2.7 v, i oh = -10 ma v dd C 0.5 v i oht output high current total for all ports 100 ma v ol output low voltage normal drive pad except reset_b 2.7 v v dd 3.6 v, i ol = 5 ma 0.5 v 1 1.71 v v dd 2.7 v, i ol = 2.5 ma 0.5 v v ol output low voltage high drive pad except reset_b 2.7 v v dd 3.6 v, i ol = 20 ma 0.5 v 1 1.71 v v dd 2.7 v, i ol = 10 ma 0.5 v v ol output low voltage reset_b table continues on the next page... general kv5x data sheet, rev. 4, 06/2016 9 nxp semiconductors
table 3. voltage and current operating behaviors (continued) symbol description min. typ. max. unit notes 2.7 v v dd 3.6 v, i ol = 3 ma 0.5 v 1.71 v v dd 2.7 v, i ol = 1.5 ma 0.5 v i olt output low current total for all ports 100 ma i in input leakage current (per pin) for full temperature range all pins other than high drive port pins 0.002 0.5 a 1 , 2 high drive port pins 0.004 0.5 a i icio io pin negative dc injection current C single pin. v in < v ss C 0.3v -3 ma 3 i iccont contiguous pin dc injection current C regional limit, includes sum of negative injection currents of 16 contiguous pins -25 ma v odpu open drain pullup voltage level v dd v dd ma 4 r pu internal pullup resistors 20 50 k 5 r pd internal pulldown resistors 20 50 k 6 1. ptb0, ptb1, ptc3, ptc4, ptd4, ptd5, ptd6, and ptd7 i/o have both high drive and normal drive capability selected by the associated ptx_pcrn[dse] control bit. all other gpios are normal drive only. 2. measured at vdd=3.6v 3. all i/o pins are internally clamped to v ss through an esd protection diode. there is no diode connection to v dd . if v in is greater than v io_min (= v ss -0.3 v), then there is no need to provide current limiting resistors at the pads. if this limit cannot be observed then a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r = (v io_min - v in )/|i icio |. 4. open drain outputs must be pulled to v dd . 5. measured at v dd supply voltage = v dd min and vinput = v ss 6. measured at v dd supply voltage = v dd min and vinput = v dd 2.2.4 power mode transition operating behaviors all specifications except t por and vllsx run recovery times in the following table assume this clock configuration: ? cpu and system clocks = 100 mhz ? bus and flash clock = 25 mhz ? fei clock mode table 4. power mode transition operating behaviors symbol description min. typ. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.71 v to execution of the 300 s table continues on the next page... general 10 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
table 4. power mode transition operating behaviors (continued) symbol description min. typ. max. unit notes first instruction across the operating temperature range of the chip. ? vlls0 run 149 s ? vlls1 run 149 s ? vlls3 run 79 s ? vlps run 5.7 s ? stop run 5.7 s 2.2.5 power consumption operating behaviors note in the following table, the maximum values represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 ). table 5. power consumption operating behaviors symbol description min. typ. max. unit notes i dda analog supply current 5 8 ma hsadc0 and hsadc1 with 66.6 mhz clock, adc0 with 25 mhz clock. i dd_run run mode current all peripheral clocks disabled, code executing from flash, while(1) loop, excludes adc idda ? @ 1.8v ? @ 3.0v 7.5 7.6 36 39 ma ma core frequency of 25 mhz i dd_run run mode current all peripheral clocks disabled, code executing from flash, while(1) loop, excludes adc idda ? @ 1.8v ? @ 3.0v 10.8 10.8 ma ma core frequency of 50 mhz table continues on the next page... general kv5x data sheet, rev. 4, 06/2016 11 nxp semiconductors
table 5. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_run run mode current all peripheral clocks disabled, code executing from flash, while(1) loop, excludes adc idda ? @ 3.0v ? @25c ? @105c 27.9 44.3 30.0 55.7 ma ma core frequency of 160 mhz. i dd_run run mode current all peripheral clocks disabled, running benchmark code from flash, excludes adc idda ? @ 3.0v ? @25c ? @105c 70.0 79.9 ma ma coremark benchmark compiled using iar 7.50 with optimization level set to high for speed with no size constraints option selected. clock frequencies configured as follows: ? core clock is 160 mhz ? fast peripher al clock is 80 mhz ? flexbus clock is 26.67 mhz ? bus/ flash clock is 26.67 mhz i dd_hsrun run mode current all peripheral clocks disabled, code executing from flash, while(1) loop, excludes adc idda ? @ 3.0v ? @25c ? @105c 43.8 62.5 47.1 80.8 ma ma core frequency of 240 mhz. i dd_hsrun run mode current all peripheral clocks enabled, code executing from flash, while(1) loop, excludes adc idda ? @ 3.0v core frequency of 240 mhz. nanoedge module at 120 mhz. table continues on the next page... general 12 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
table 5. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes ? @ 25c ? @ 105c 70.8 92.3 74.1 107.9 ma ma i dd_hsrun hsrun mode current all peripheral clocks disabled, running benchmark code from flash, excludes adc idda ? @ 3.0v ? @ 25c ? @ 105c 116 132.9 ma ma coremark benchmark compiled using iar 7.50 with optimization level set to high for speed with no size constraints option selected. clock frequencies configured as follows: ? core clock is 240 mhz ? fast peripher al clock is 120 mhz ? flexbus clock is 30 mhz ? bus/ flash clock is 24 mhz i dd_wait wait mode high frequency current at 3.0 v all peripheral clocks disabled 16.3 ma 160 mhz pee mode, fast peripheral clock = 80 mhz, flexbus clock = 80 mhz, bus/ flash clock = 20 mhz i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks disabled 0.729 7.6 ma cpu frequency 4 mhz i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks enabled 1.2 9.4 ma cpu frequency 4 mhz i dd_vlpw very-low-power wait mode current at 3.0 v all peripheral clocks disabled 0.33 0.43 ma 4 mhz system/ core clock, fast peripheral clock, and flexbus clock. table continues on the next page... general kv5x data sheet, rev. 4, 06/2016 13 nxp semiconductors
table 5. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes 1 mhz bus/ flash clock. all peripheral clocks disabled. temp = 25c. i dd_stop stop mode current at 3.0 v ? @ C40 to 25c ? @ 105c 0.55 11.1 0.91 18.3 ma ma i dd_vlps very-low-power stop mode current at 3.0 v ? @ C40 to 25c ? @ 105c 0.107 4.0 0.33 7.6 ma ma i dd_vlls3 very low-leakage stop mode 3 current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 5.2 29.8 122.4 8.6 85 185 a a a i dd_vlls2 very low-leakage stop mode 2 current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 3.2 11.6 47.2 4.8 45 71 a a a i dd_vlls1 very low-leakage stop mode 1 current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 0.778 3.9 18.8 2.6 21 36 a a a i dd_vlls0b very low-leakage stop mode 0 current at 3.0 v with por detect circuit enabled ? @ C40 to 25c ? @ 70c ? @ 105c 0.5 3.4 18.2 2.1 21 36 a a a i dd_vlls0a very low-leakage stop mode 0 current at 3.0 v with por detect circuit disabled ? @ C40 to 25c ? @ 70c ? @ 105c 0.147 3.0 17.6 1.69 16.8 29.2 a a a general 14 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
table 6. low power mode peripheral adders typical value symbol description temperature (c) unit -40 25 50 70 85 105 i irefsten4mhz 4 mhz internal reference clock (irc) adder. measured by entering stop or vlps mode with 4 mhz irc enabled. 56 56 56 56 56 56 a i irefsten32khz 32 khz internal reference clock (irc) adder. measured by entering stop mode with the 32 khz irc enabled. 52 52 52 52 52 52 a i erefsten4mhz external 4 mhz crystal clock adder. measured by entering stop or vlps mode with the crystal enabled. 206 228 237 245 251 258 ua i erefsten32khz external 32 khz crystal clock adder by means of the osc0_cr[erefsten and erefsten] bits. measured by entering all modes with the crystal enabled. vlls1 vlls3 lls vlps stop 440 440 490 510 510 490 490 490 560 560 540 540 540 560 560 560 560 560 560 560 570 570 570 610 610 580 580 680 680 680 na i cmp cmp peripheral adder measured by placing the device in vlls1 mode with cmp enabled using the 6-bit dac and a single external input for compare. includes 6-bit dac power consumption. 22 22 22 22 22 22 a i uart uart peripheral adder measured by placing the device in stop or vlps mode with selected clock source waiting for rx data at 115200 baud rate. includes selected clock source power consumption. mcgirclk (4 mhz internal reference clock) oscerclk (4 mhz external crystal) 66 214 66 234 66 246 66 254 66 260 66 268 a i bg bandgap adder when bgen bit is set and device is placed in vlpx, lls, or vllsx mode. 45 45 45 45 45 45 a general kv5x data sheet, rev. 4, 06/2016 15 nxp semiconductors
2.2.6 emc radiated emissions operating behaviors table 7. emc radiated emissions operating behaviors symbol conditions clocks frequency band (mhz) typ. unit notes v eme device configuration, test conditions and em testing per standard iec 61967-2. ? supply voltage vdd = 3.3 v ? temperature = 25 c ? f osc = 20 mhz (crystal) ? f sys = 150 mhz 0.15C50 14 dbv 1 50C150 25 dbv 150C500 23 dbv 500C1000 16 dbv 0.15C1000 k 2 1. determined according to iec standard 61967-1, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 1: general conditions and definitions and iec standard 61967-2, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 2: measurement of radiated emissionstem cell and wideband tem cell method . measurements were made while the microcontroller was running basic application code. the reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. specified according to annex d of iec standard 61967-2, measurement of radiated emissionstem cell and wideband tem cell method 2.2.7 designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to www.nxp.com . 2. perform a keyword search for emc design. 2.2.8 capacitance attributes table 8. capacitance attributes symbol description min. max. unit c in_a input capacitance: analog pins 7 pf c in_d input capacitance: digital pins 7 pf 2.3 switching specifications general 16 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
2.3.1 typical device clock specifications table 9. device clock specifications symbol description min. max. unit notes high speed run mode f sys system (cpu) clock 240 mhz normal run mode (and high speed run mode unless otherwise specified above) f sys system (cpu) clock 160 mhz f fastperipheral fast peripheral clock 120 mhz 1 fb_clk flexbus clock 60 mhz f bus_flash bus / flash clock 27.5 mhz f lptmr lptmr clock 24 mhz vlpr mode f sys system (cpu) clock 4 mhz f fastperipheral fast peripheral clock 4 mhz fb_clk flexbus clock 4 mhz f bus_flash bus / flash clock 500 khz f erclk external reference clock 16 mhz f lptmr lptmr clock 24 mhz 2 1. when using this clock to supply the nano-edge module, this clock must be 1/2 of the system clock. 2. the lptmr can be clocked at this speed in vlpr or vlps only when the source is a clock input connected to the extal pin with the osc configured for bypass (external clock) operation. 2.3.2 general switching specifications these general purpose specifications apply to all signals configured for gpio, uart, flexcan, and i 2 c signals. table 10. general switching specifications description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 gpio pin interrupt pulse width (digital glitch filter enabled, analog filter disabled) asynchronous path 80 ns 2 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) asynchronous path 50 ns 2 external reset and nmi pin interrupt pulse width asynchronous path 100 ns 2 gpio pin interrupt pulse width asynchronous path 10 ns 2 normal drive fast pins ? 2.7 vdd 3.6 v 3 , 4 table continues on the next page... general kv5x data sheet, rev. 4, 06/2016 17 nxp semiconductors
table 10. general switching specifications (continued) description min. max. unit notes ? fast slew rate ? slow slew rate ? 1.71 vdd < 2.7 v ? fast slew rate ? slow slew rate 0.7 16 2.15 16 ns ns high drive fast pins (normal/low drive enabled) ? 2.7 vdd 3.6 v ? fast slew rate ? slow slew rate ? 1.71 vdd < 2.7 v ? fast slew rate ? slow slew rate 0.7 15.65 2.35 35.3 ns ns 3 , 5 high drive fast pins (high drive enabled) ? 2.7 vdd 3.6 v ? fast slew rate ? slow slew rate ? 1.71 vdd < 2.7 v ? fast slew rate ? slow slew rate 3 16.5 6.5 36.3 ns ns 1. the synchronous and asynchronous timing must be met. 2. this is the shortest pulse that is guaranteed to be recognized. 3. for high drive pins with high drive enabled, load is 75pf; other pins load (normal/low drive) is 25pf. fast slew rate is enabled by clearing portx_pcrn[sre]. 4. normal drive fast pins: all other gpio pins that are not high drive fast pins. 5. high drive fast pins: ptb0, ptb1, ptc3, ptc4, ptd4, ptd5, ptd6, and ptd7. high drive capability is enabled by setting portx_pcrn[dse] 2.4 thermal specifications 2.4.1 thermal operating requirements table 11. thermal operating requirements symbol description min. max. unit notes t j die junction temperature C40 125 c t a ambient temperature C40 105 c 1 1. maximum t a can be exceeded only if the user ensures that t j does not exceed maximum t j . the simplest method to determine t j is: t j = t a + r ja x chip power dissipation general 18 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
2.4.2 thermal attributes table 12. thermal attributes board type symbol description 144 mapbg a 1 144 lqfp 100 lqfp unit notes single-layer (1s) r ja thermal resistance, junction to ambient (natural convection) 51 51 c/w 2 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 42 38 c/w single-layer (1s) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 42 41 c/w four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 36 32 c/w r jb thermal resistance, junction to board 30 23 c/w 3 r jc thermal resistance, junction to case 11 10 c/w 4 jt thermal characterization parameter, junction to package top outside center (natural convection) 2 2 c/w 5 1. package your way 2. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) , or eia/jedec standard jesd51-6, integrated circuit thermal test method environmental conditionsforced convection (moving air) . 3. determined according to jedec standard jesd51-8, integrated circuit thermal test method environmental conditionsjunction-to-board . 4. determined according to method 1012.1 of mil-std 883, test method standard, microcircuits , with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. 5. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) . 3 peripheral operating requirements and behaviors 3.1 core modules peripheral operating requirements and behaviors kv5x data sheet, rev. 4, 06/2016 19 nxp semiconductors
3.1.1 swd electricals table 13. swd full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v j1 swd_clk frequency of operation ? serial wire debug 0 25 mhz j2 swd_clk cycle period 1/j1 ns j3 swd_clk clock pulse width ? serial wire debug 20 ns j4 swd_clk rise and fall times 3 ns j9 swd_dio input data setup time to swd_clk rise 10 ns j10 swd_dio input data hold time after swd_clk rise 0 ns j11 swd_clk high to swd_dio data valid 32 ns j12 swd_clk high to swd_dio high-z 5 ns j2 j3 j3 j4 j4 swd_clk (input) figure 3. serial wire clock input timing peripheral operating requirements and behaviors 20 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
j11 j12 j11 j9 j10 input data valid output data valid output data valid swd_clk swd_dio swd_dio swd_dio swd_dio figure 4. serial wire data timing 3.1.2 debug trace timing specifications table 14. debug trace operating behaviors symbol description min. max. unit t cyc clock period frequency dependent mhz t wl low pulse width 2 ns t wh high pulse width 2 ns t r clock and data rise time 3 ns t f clock and data fall time 3 ns t s data setup 3 1.5 ns t h data hold 2 1.0 ns peripheral operating requirements and behaviors kv5x data sheet, rev. 4, 06/2016 21 nxp semiconductors
traceclk t r t wh t f t cyc t wl figure 5. trace_clkout specifications th ts ts th trace_clkout trace_d[3:0] figure 6. trace data specifications 3.1.3 jtag electricals table 15. jtag limited voltage range electricals symbol description min. max. unit operating voltage 2.7 3.6 v j1 tclk frequency of operation ? boundary scan ? jtag and cjtag ? serial wire debug 0 0 0 10 25 50 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width ? boundary scan ? jtag and cjtag ? serial wire debug 50 20 10 ns ns ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 2.0 ns j7 tclk low to boundary scan output data valid 28 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1 ns table continues on the next page... peripheral operating requirements and behaviors 22 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
table 15. jtag limited voltage range electricals (continued) symbol description min. max. unit j11 tclk low to tdo data valid 19 ns j12 tclk low to tdo high-z 17 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns table 16. jtag full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v j1 tclk frequency of operation ? boundary scan ? jtag and cjtag ? serial wire debug 0 0 0 10 20 40 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width ? boundary scan ? jtag and cjtag ? serial wire debug 50 25 12.5 ns ns ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 2.0 ns j7 tclk low to boundary scan output data valid 30.6 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1.0 ns j11 tclk low to tdo data valid 19.0 ns j12 tclk low to tdo high-z 17.0 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns j2 j3 j3 j4 j4 tclk (input) figure 7. test clock input timing peripheral operating requirements and behaviors kv5x data sheet, rev. 4, 06/2016 23 nxp semiconductors
j7 j8 j7 j5 j6 input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs figure 8. boundary scan (jtag) timing j11 j12 j11 j9 j10 input data valid output data valid output data valid tclk tdi/tms tdo tdo tdo figure 9. test access port timing peripheral operating requirements and behaviors 24 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
j14 j13 tclk trst figure 10. trst timing 3.2 system modules there are no specifications necessary for the device's system modules. 3.3 clock modules 3.3.1 mcg specifications table 17. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal vdd and 25 c 32.768 khz f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz fdco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim and scftrim 0.3 0.6 %f dco 1 f dco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim only 0.2 0.5 %f dco 1 f dco_t total deviation of trimmed average dco output frequency over voltage and temperature 0.5 2 %f dco 1 , f dco_t total deviation of trimmed average dco output frequency over fixed voltage and temperature range of 0C70c 1 %f dco 1 f intf_ft internal reference frequency (fast clock) factory trimmed at nominal vdd and 25c 4 mhz f intf_t internal reference frequency (fast clock) user trimmed at nominal vdd and 25 c 3 5 mhz f loc_low loss of external clock minimum frequency range = 00 (3/5) x f ints_t khz table continues on the next page... peripheral operating requirements and behaviors kv5x data sheet, rev. 4, 06/2016 25 nxp semiconductors
table 17. mcg specifications (continued) symbol description min. typ. max. unit notes f loc_high loss of external clock minimum frequency range = 01, 10, or 11 (16/5) x f ints_t khz fll f fll_ref fll reference frequency range 31.25 39.0625 khz f dco dco output frequency range low range (drs=00) 640 f fll_ref 20 20.97 25 mhz 2 , 3 mid range (drs=01) 1280 f fll_ref 40 41.94 50 mhz mid-high range (drs=10) 1920 f fll_ref 60 62.91 75 mhz high range (drs=11) 2560 f fll_ref 80 83.89 100 mhz f dco_t_dmx3 2 dco output frequency low range (drs=00) 732 f fll_ref 23.99 mhz 4 , 5 mid range (drs=01) 1464 f fll_ref 47.97 mhz mid-high range (drs=10) 2197 f fll_ref 71.99 mhz high range (drs=11) 2929 f fll_ref 95.98 mhz j cyc_fll fll period jitter ? f dco = 48 mhz ? f dco = 98 mhz 180 150 ps t fll_acquire fll target frequency acquisition time 1 ms 6 pll f pll_ref pll reference frequency range 8 16 mhz f vcoclk_2x vco output frequency 220 480 mhz f vcoclk pll output frequency 110 240 mhz f vcoclk_90 pll quadrature output frequency 110 240 mhz i pll pll operating current ? vco @ 176 mhz (f osc_hi_1 = 32 mhz, f pll_ref = 8 mhz, vdiv multiplier = 22) 2.8 ma 7 i pll pll operating current ? vco @ 360 mhz (f osc_hi_1 = 32 mhz, f pll_ref = 8 mhz, vdiv multiplier = 45) 4.7 ma 7 j cyc_pll pll period jitter (rms) ? f vco = 48 mhz ? f vco = 120 mhz 120 75 ps ps 8 j acc_pll pll accumulated jitter over 1s (rms) 8 table continues on the next page... peripheral operating requirements and behaviors 26 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
table 17. mcg specifications (continued) symbol description min. typ. max. unit notes ? f vco = 48 mhz ? f vco = 120 mhz 1350 600 ps ps d unl lock exit frequency tolerance 4.47 5.97 % t pll_lock lock detector detection time 150 10 -6 + 1075(1/ f pll_ref ) s 9 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=0. 3. the resulting system clock frequencies should not exceed their maximum specified values. the dco frequency deviation ( f dco_t ) over voltage and temperature should be considered. 4. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=1. 5. the resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. this specification applies to any time the fll reference source or reference divider is changed, trim value is changed, dmx32 bit is changed, drs bits are changed, or changing from fll disabled (blpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. excludes any oscillator currents that are also consuming power while pll is in operation. 8. this specification was obtained using a nxp developed pcb. pll jitter is dependent on the noise characteristics of each pcb and results will vary. 9. this specification applies to any time the pll vco divider or reference divider is changed, or changing from pll disabled (blpe, blpi) to pll enabled (pbe, pee). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 3.3.2 oscillator electrical specifications 3.3.2.1 oscillator dc electrical specifications table 18. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) ? 32 khz ? 4 mhz ? 8 mhz ? 16 mhz ? 24 mhz ? 32 mhz 500 200 300 950 1.2 1.5 na a a a ma ma 1 i ddosc supply current high gain mode (hgo=1) ? 4 mhz 400 a 1 table continues on the next page... peripheral operating requirements and behaviors kv5x data sheet, rev. 4, 06/2016 27 nxp semiconductors
table 18. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes ? 8 mhz ? 16 mhz ? 24 mhz ? 32 mhz 500 2.5 3 4 a ma ma ma c x extal load capacitance 2 , 3 c y xtal load capacitance 2 , 3 r f feedback resistor low-frequency, low-power mode (hgo=0) m 2 , 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m feedback resistor high-frequency, low- power mode (hgo=0) m feedback resistor high-frequency, high-gain mode (hgo=1) 1 m r s series resistor low-frequency, low-power mode (hgo=0) k series resistor low-frequency, high-gain mode (hgo=1) 200 k series resistor high-frequency, low-power mode (hgo=0) k series resistor high-frequency, high-gain mode (hgo=1) 0 k v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 c 2. see crystal or resonator manufacturer's recommendation 3. c x ,c y can be provided by using the integrated capacitors when the low frequency oscillator (range = 00) is used. for all other cases external capacitors must be used. 4. when low power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other devices. peripheral operating requirements and behaviors 28 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
3.3.2.2 oscillator frequency specifications table 19. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low- frequency mode (mcg_c2[range]=00) 32 40 khz f ec_extal input clock frequency (external clock mode) 48 mhz 1 , 2 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) 1000 ms 3 , 4 1. other frequency limits may apply when external clock is being used as a reference for the fll or pll. 2. when transitioning from fei or fbi to fbe mode, restrict the frequency of the input clock so that, when it is divided by frdiv, it remains within the limits of the dco input clock frequency. 3. proper pc board layout procedures must be followed to achieve specifications. 4. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. note the 32 khz oscillator works in low power mode by default and cannot be moved into high power/gain mode. 3.4 memories and memory interfaces 3.4.1 flash (ftfe) electrical specifications this section describes the electrical characteristics of the ftfe module. note all flash programerase functions can only be performed when the mcu is in normal run mode. programming or erasing the flash in hsrun mode is not allowed. 3.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 20. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm8 program phrase high-voltage time 7.5 18 s t hversscr erase flash sector high-voltage time 13 113 ms 1 table continues on the next page... peripheral operating requirements and behaviors kv5x data sheet, rev. 4, 06/2016 29 nxp semiconductors
table 20. nvm program/erase timing specifications (continued) symbol description min. typ. max. unit notes t hversall1m erase all blocks high-voltage time for 1 mb 832 7232 ms 1 1. maximum time based on expectations at cycling end-of-life. 3.4.1.2 flash timing specifications commands table 21. flash command timing specifications symbol description min. typ. max. unit notes t rd1sec8k read 1s section execution time (8 kb flash) 200 s 1 t pgmchk program check execution time 95 s 1 t rdrsrc read resource execution time 40 s 1 t pgm8 program phrase execution time 90 150 s t ersscr erase flash sector execution time 15 115 ms 2 t pgmsec1k program section execution time (1kb flash) 5 ms t rd1allx read 1s all blocks execution time 1.8 ms t rdonce read once execution time 30 s 1 t pgmonce program once execution time 90 s t ersall erase all blocks execution time 870 7400 ms 2 t vfykey verify backdoor access key execution time 30 s 1 t ersallu erase all blocks unsecure execution time 870 7400 ms 2 1. assumes 25mhz or greater flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 3.4.1.3 flash high voltage current behaviors table 22. flash high voltage current behaviors symbol description min. typ. max. unit i dd_pgm average current adder during high voltage flash programming operation 3.5 7.5 ma i dd_ers average current adder during high voltage flash erase operation 1.5 4.0 ma peripheral operating requirements and behaviors 30 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
3.4.1.4 reliability specifications table 23. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years t nvmretp1k data retention after up to 1 k cycles 20 100 years n nvmcycp cycling endurance 10 k 50 k cycles 2 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at -40c t j 125c. 3.5 flexbus switching specifications all processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, fb_clk. the fb_clk frequency may be the same as the internal system bus frequency or an integer divider of that frequency. the following timing numbers indicate when data is latched or driven onto the external bus, relative to the flexbus output clock (fb_clk). all other timing relationships can be derived from these values. table 24. flexbus limited voltage range switching specifications num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation fb_clk mhz fb1 clock period 1/fb_clk ns fb2 address, data, and control output valid 11.8 ns fb3 address, data, and control output hold 1.0 ns 1 fb4 data and fb_ta input setup 11.9 ns fb5 data and fb_ta input hold 0.0 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n , fb_cs n , fb_oe, fb_r/ w, fb_tbst, fb_tsiz[1:0], fb_ale, and fb_ts. 2. specification is valid for all fb_ad[31:0] and fb_ta. table 25. flexbus full voltage range switching specifications num description min. max. unit notes operating voltage 1.71 3.6 v table continues on the next page... peripheral operating requirements and behaviors kv5x data sheet, rev. 4, 06/2016 31 nxp semiconductors
table 25. flexbus full voltage range switching specifications (continued) num description min. max. unit notes frequency of operation fb_clk mhz fb1 clock period 1/fb_clk ns fb2 address, data, and control output valid 12.6 ns fb3 address, data, and control output hold 1.0 ns 1 fb4 data and fb_ta input setup 12.5 ns fb5 data and fb_ta input hold 0 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n , fb_cs n , fb_oe, fb_r/ w, fb_tbst, fb_tsiz[1:0], fb_ale, and fb_ts. 2. specification is valid for all fb_ad[31:0] and fb_ta. peripheral operating requirements and behaviors 32 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
address address data tsiz aa=1 aa=0 aa=1 aa=0 fb3 fb5 fb4 fb4 fb5 fb1 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] fb2 read timing parameters electricals_read.svg s0 s1 s2 s3 s0 s0 s1 s2 s3 s0 figure 11. flexbus read timing diagram peripheral operating requirements and behaviors kv5x data sheet, rev. 4, 06/2016 33 nxp semiconductors
address address data tsiz aa=1 aa=0 aa=1 aa=0 fb1 fb3 fb4 fb5 fb2 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] write timing parameters electricals_write.svg figure 12. flexbus write timing diagram 3.6 security and integrity modules there are no specifications necessary for the device's security and integrity modules. 3.7 analog peripheral operating requirements and behaviors 34 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
3.7.1 12-bit sar high speed analog-to-digital converter (hsadc) parameters table 26. 12-bit hsadc electrical specifications characteristic symbol min typ max unit recommended operating conditions analog supply voltage v dda 1.71 3.6 v v refh supply voltage ? v dda 2v ? v dda < 2v v refh 2.0 v dda v dda v dda v v refl supply voltage v refl v ssa v ssa 0.1 v analog input full-scale input range (single-ended mode) v refl v refh v full-scale input range (differential mode) 2*(v refh - v refl ) v input signal common mode (only for differential mode) (v refh + v refl )/2 v input sampling capacitance (no parasitic capacitances included) c s 5 pf current consumption fs=5msps (conversion in progress, differential mode) 1 ? i dda ? i dd 1150 85 a fs=1msps (conversion in progress, differential mode) 1 ? i dda ? i dd 260 19 a fs=10ksps (conversion in progress, differential mode) 1 ? i dda ? i dd 19 2.9 a fs=5msps (conversion in progress, single- ended mode) 1 ? i dda ? i dd 1030 85 a fs=1msps (conversion in progress, single- ended mode) 1 ? i dda ? i dd 230 18 a fs=10ksps (conversion in progress, single- ended mode) 1 a table continues on the next page... peripheral operating requirements and behaviors kv5x data sheet, rev. 4, 06/2016 35 nxp semiconductors
table 26. 12-bit hsadc electrical specifications (continued) characteristic symbol min typ max unit ? i dda ? i dd 19 2.9 fs=5msps (conversion not in progress) ? i dda ? i dd 38 57 a fs=1msps (conversion not in progress) ? i dda ? i dd 22 14 a fs=10ksps (conversion not in progress) ? i dda ? i dd 19 2.7 a timing characteristics input clock frequency f clk 0.14 70 80 mhz input clock frequency during calibration f clk 0.14 60 mhz sampling rate 2 ? adcres=11 (12 bits conversion result) ? adcres=10 (10 bits conversion result) ? adcres=01 (8 bits conversion result) ? adcres=00 (6 bits conversion result) f s 0.01 0.012 0.014 0.0175 5 5.83 7 8.75 5.71 6.66 8 10 msps conversion cycle 2 (back to back) ? adcres=11 (12 bits conversion result) ? adcres=10 (10 bits conversion result) ? adcres=01 (8 bits conversion result) ? adcres=00 (6 bits conversion result) 14 12 10 8 clock cycles data latency 2 ? adcres=11 (12 bits conversion result) ? adcres=10 (10 bits conversion result) ? adcres=01 (8 bits conversion result) ? adcres=00 (6 bits conversion result) 12.5 10.5 8.5 6.5 clock cycles accuracy (dc or absolute) integral non-linearity inl +/- 3.0 lsb differential non-linearity dnl +/- 1.0 lsb table continues on the next page... peripheral operating requirements and behaviors 36 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
table 26. 12-bit hsadc electrical specifications (continued) characteristic symbol min typ max unit signal-to-noise and distortion ratio 3 sinad 65 dbfs offset error (calibration enabled) +/- 2.0 lsb offset error (calibration disabled) +/- 64 lsb total unadjusted error (calibration enabled) tue +/- 5 lsb 1. successive conversion mode 2. "adcres" refers to the resolution selection control signal 3. value measured with a C0.5dbfs input signal and then extrapolated to full scale. 3.7.2 adc electrical specifications the 16-bit accuracy specifications listed in table 1 and table 28 are achievable on the differential pins adcx_dp0, adcx_dm0. all other adc channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 3.7.2.1 16-bit adc operating conditions table 27. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v dda supply voltage delta to v dd (v dd C v dda ) -100 0 +100 mv 2 v ssa ground voltage delta to v ss (v ss C v ssa ) -100 0 +100 mv 2 v refh adc reference voltage high 1.13 v dda v dda v v refl adc reference voltage low v ssa v ssa v ssa v v adin input voltage v refl v refh v c adin input capacitance ? 16-bit mode ? 8-bit / 10-bit / 12-bit modes 8 4 10 5 pf r adin input series resistance 2 5 k r as analog source resistance (external) 13-bit / 12-bit modes f adck < 4 mhz 5 k 3 table continues on the next page... peripheral operating requirements and behaviors kv5x data sheet, rev. 4, 06/2016 37 nxp semiconductors
table 27. 16-bit adc operating conditions (continued) symbol description conditions min. typ. 1 max. unit notes f adck adc conversion clock frequency 13-bit mode 1.0 24.0 mhz 4 f adck adc conversion clock frequency 16-bit mode 2.0 12.0 mhz 4 c rate adc conversion rate 13-bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20.000 818.330 ksps 5 c rate adc conversion rate 16-bit mode no adc hardware averaging continuous conversions enabled, subsequent conversion time 37.037 461.467 ksps 5 1. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 1.0 mhz, unless otherwise stated. typical values are for reference only, and are not tested in production. 2. dc potential difference. 3. this resistance is external to mcu. to achieve the best results, the analog source resistance must be kept as low as possible. the results in this data sheet were derived from a system that had < 8 analog source resistance. the r as /c as time constant should be kept to < 1 ns. 4. to use the maximum adc conversion clock frequency, cfg2[adhsc] must be set and cfg1[adlpc] must be clear. 5. for guidelines and examples of conversion rate calculation, download the adc calculator tool . peripheral operating requirements and behaviors 38 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
r as v as c as z as v adin z adin r adin r adin r adin r adin c adin pad leakage due to input protection input pin input pin input pin simplified input pin equivalent circuit simplified channel select circuit adc sar engine figure 13. adc input impedance equivalency diagram 3.7.2.2 16-bit adc electrical characteristics table 28. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 min. typ. 2 max. unit notes i dda_adc supply current 0.215 1.7 ma 3 f adack adc asynchronous clock source ? adlpc = 1, adhsc = 0 ? adlpc = 1, adhsc = 1 ? adlpc = 0, adhsc = 0 ? adlpc = 0, adhsc = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 mhz mhz mhz mhz t adack = 1/ f adack sample time see reference manual chapter for sample times tue total unadjusted error ? 12-bit modes ? <12-bit modes 4 1.4 6.8 2.1 lsb 4 5 dnl differential non- linearity ? 12-bit modes ? <12-bit modes 0.7 0.2 C1.1 to +1.9 C0.3 to 0.5 lsb 4 5 inl integral non-linearity ? 12-bit modes 1.0 C2.7 to +1.9 lsb 4 5 table continues on the next page... peripheral operating requirements and behaviors kv5x data sheet, rev. 4, 06/2016 39 nxp semiconductors
table 28. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes ? <12-bit modes 0.5 C0.7 to +0.5 e fs full-scale error ? 12-bit modes ? <12-bit modes C4 C1.4 C5.4 C1.8 lsb 4 v adin = v dda 5 e q quantization error ? 16-bit modes ? 13-bit modes C1 to 0 0.5 lsb 4 enob effective number of bits 16-bit differential mode ? avg = 32 ? avg = 4 16-bit single-ended mode ? avg = 32 ? avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits 6 sinad signal-to-noise plus distortion see enob 6.02 enob + 1.76 db thd total harmonic distortion 16-bit differential mode ? avg = 32 16-bit single-ended mode ? avg = 32 -94 -85 db db 7 sfdr spurious free dynamic range 16-bit differential mode ? avg = 32 16-bit single-ended mode ? avg = 32 82 78 95 90 db db 7 e il input leakage error i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) temp sensor slope across the full temperature range of the device 1.55 1.62 1.69 mv/c 8 v temp25 temp sensor voltage 25 c 706 716 726 mv 8 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. peripheral operating requirements and behaviors 40 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
3. the adc supply current depends on the adc conversion clock speed, conversion rate and adc_cfg1[adlpc] (low power). for lowest power operation, adc_cfg1[adlpc] must be set, the adc_cfg2[adhsc] bit must be clear with 1 mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock < 16 mhz, max hardware averaging (avge = %1, avgs = %11) 6. input data is 100 hz sine wave. adc conversion clock < 12 mhz. 7. input data is 1 khz sine wave. adc conversion clock < 12 mhz. 8. adc conversion clock < 3 mhz typical adc 16-bit differential enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 15.00 14.70 14.40 14.10 13.80 13.50 13.20 12.90 12.60 12.30 12.00 1 2 3 4 5 6 7 8 9 10 1211 hardware averaging disabled averaging of 4 samples averaging of 8 samples averaging of 32 samples figure 14. typical enob vs. adc_clk for 16-bit differential mode typical adc 16-bit single-ended enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 14.00 13.75 13.25 13.00 12.75 12.50 12.00 11.75 11.50 11.25 11.00 1 2 3 4 5 6 7 8 9 10 1211 averaging of 4 samples averaging of 32 samples 13.50 12.25 figure 15. typical enob vs. adc_clk for 16-bit single-ended mode peripheral operating requirements and behaviors kv5x data sheet, rev. 4, 06/2016 41 nxp semiconductors
3.7.3 cmp and 6-bit dac electrical specifications table 29. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en = 1, pmode = 1) 200 a i ddls supply current, low-speed mode (en = 1, pmode = 0) 20 a v ain analog input voltage v ss v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 ? cr0[hystctr] = 00 ? cr0[hystctr] = 01 ? cr0[hystctr] = 10 ? cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd C 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en = 1, pmode = 1) 20 50 200 ns t dls propagation delay, low-speed mode (en = 1, pmode = 0) 80 250 600 ns analog comparator initialization delay 2 40 s i dac6b 6-bit dac current adder (enabled) 7 a inl 6-bit dac integral non-linearity C0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity C0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.7 to v dd C 0.7 v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to dacen, vrsel, psel, msel, vosel) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 peripheral operating requirements and behaviors 42 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
cmp hysteresis vs vinn 0 1 2 hystctr setting 000.00e+00 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 vinn (v) 3 30.00e-03 20.00e-03 10.00e-03 40.00e-03 50.00e-03 60.00e-03 70.00e-03 80.00e-03 90.00e-03 cmp hysteresis (v) figure 16. typical hysteresis vs. vin level (v dd = 3.3 v, pmode = 0) 180.00e-03 cmp hysteresis vs vinn 0 1 2 hystctr setting 60.00e-03 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cmp hysteresis (v) vinn (v) 3 -20.00e-03 000.00e+00 20.00e-03 40.00e-03 80.00e-03 100.00e-03 120.00e-03 140.00e-03 160.00e-03 figure 17. typical hysteresis vs. vin level (v dd = 3.3 v, pmode = 1) 3.7.4 12-bit dac electrical characteristics peripheral operating requirements and behaviors kv5x data sheet, rev. 4, 06/2016 43 nxp semiconductors
3.7.4.1 12-bit dac operating requirements table 30. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 3.6 v v dacr reference voltage 1.13 3.6 v 1 c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be v dda or v refh . 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac. 3.7.4.2 12-bit dac operating behaviors table 31. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_dacl p supply current low-power mode 150 a i dda_dach p supply current high-speed mode 700 a t daclp full-scale settling time (0x080 to 0xf7f) low-power mode 100 200 s 1 t dachp full-scale settling time (0x080 to 0xf7f) high-power mode 15 30 s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) ? high-speed mode ? low speed mode 1 5 s 1 v dacoutl dac output voltage range low high- speed mode, no load, dac set to 0x000 100 mv v dacouth dac output voltage range high high- speed mode, no load, dac set to 0xfff v dacr ?100 v dacr mv inl integral non-linearity error high speed mode 8 lsb 2 dnl differential non-linearity error v dacr > 2 v 1 lsb 3 dnl differential non-linearity error v dacr = vref_out 1 lsb 4 v offset offset error 0.4 0.8 %fsr 5 e g gain error 0.1 0.6 %fsr 5 psrr power supply rejection ratio, v dda 2.4 v 60 90 db t co temperature coefficient offset voltage 3.7 v/c 6 t ge temperature coefficient gain error 0.000421 %fsr/c rop output resistance (load = 3 k) 250 sr slew rate -80h f7fh 80h v/s table continues on the next page... peripheral operating requirements and behaviors 44 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
table 31. 12-bit dac operating behaviors (continued) symbol description min. typ. max. unit notes ? high power (sp hp ) ? low power (sp lp ) 1.2 0.05 1.7 0.12 bw 3db bandwidth ? high power (sp hp ) ? low power (sp lp ) 550 40 khz 1. settling within 1 lsb 2. the inl is measured for 0 + 100 mv to v dacr ?100 mv 3. the dnl is measured for 0 + 100 mv to v dacr ?100 mv 4. the dnl is measured for 0 + 100 mv to v dacr ?100 mv with v dda > 2.4 v 5. calculated by a best fit curve from v ss + 100 mv to v dacr ? 100 mv 6. v dda = 3.0 v, reference select set for v dda (dacx_co:dacrfs = 1), high power mode (dacx_c0:lpen = 0), dac set to 0x800, temperature range is across the full range of the device digital code dac12 inl (lsb) 0 500 1000 1500 2000 2500 3000 3500 4000 2 4 6 8 -2 -4 -6 -8 0 figure 18. typical inl error vs. digital code peripheral operating requirements and behaviors kv5x data sheet, rev. 4, 06/2016 45 nxp semiconductors
temperature c dac12 mid level code voltage 25 55 85 105 125 1.499 -40 1.4985 1.498 1.4975 1.497 1.4965 1.496 figure 19. offset at half scale vs. temperature 3.8 timers see general switching specifications . 3.8.1 enhanced nanoedge pwm characteristics table 32. nanoedge pwm timing parameters characteristic symbol min typ max unit pwm clock frequency 80 120 mhz nanoedge placement (nep) step size 1 ? @ 80 mhz ? @ 120 mhz pwmp 390 260 ps power-up time 2 t pu 25 s peripheral operating requirements and behaviors 46 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
1. temperature and voltage variations do not affect nanoedge placement step size. 2. powerdown to nanoedge mode transition. 3.9 communication interfaces 3.9.1 can switching specifications see general switching specifications . 3.9.2 ethernet switching specifications the following timing specs are defined at the chip i/o pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 3.9.2.1 mii signal switching specifications the following timing specs meet the requirements for mii style interfaces for a range of transceiver devices. table 33. mii signal switching specifications symbol description min. max. unit operating voltage 1.71 3.6 v rxclk frequency 25 mhz mii1 rxclk pulse width high 35% 65% rxclk period mii2 rxclk pulse width low 35% 65% rxclk period mii3 rxd[3:0], rxdv, rxer to rxclk setup 5 ns mii4 rxclk to rxd[3:0], rxdv, rxer hold 5 ns txclk frequency 25 mhz mii5 txclk pulse width high 35% 65% txclk period mii6 txclk pulse width low 35% 65% txclk period mii7 txclk to txd[3:0], txen, txer invalid 2 ns mii8 txclk to txd[3:0], txen, txer valid 25 ns peripheral operating requirements and behaviors kv5x data sheet, rev. 4, 06/2016 47 nxp semiconductors
mii7mii8 valid data valid data valid data mii6 mii5 txclk (input) txd[n:0] txen txer figure 20. rmii/mii transmit signal timing diagram mii2 mii1 mii4mii3 valid data valid data valid data rxclk (input) rxd[n:0] rxdv rxer figure 21. rmii/mii receive signal timing diagram 3.9.2.2 rmii signal switching specifications the following timing specs meet the requirements for rmii style interfaces for a range of transceiver devices. table 34. rmii signal switching specifications num description min. max. unit operating voltage 1.71 3.6 extal frequency (rmii input clock rmii_clk) 50 mhz rmii1 rmii_clk pulse width high 35% 65% rmii_clk period rmii2 rmii_clk pulse width low 35% 65% rmii_clk period rmii3 rxd[1:0], crs_dv, rxer to rmii_clk setup 4 ns rmii4 rmii_clk to rxd[1:0], crs_dv, rxer hold 2 ns table continues on the next page... peripheral operating requirements and behaviors 48 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
table 34. rmii signal switching specifications (continued) num description min. max. unit rmii7 rmii_clk to txd[1:0], txen invalid 4 ns rmii8 rmii_clk to txd[1:0], txen valid 15.4 ns 3.9.3 dspi switching specifications (limited voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provide dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 35. master mode dspi timing (limited voltage range) num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 30 mhz ds1 dspi_sck output cycle time 2 x t bus ns ds2 dspi_sck output high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds3 dspi_pcs n to dspi_sck output valid (t bus x 2) ? 2 ns 1 ds4 dspi_sck to dspi_pcs n output hold (t bus x 2) ? 2 ns 2 ds5 dspi_sck to dspi_sout valid 8.5 ns ds6 dspi_sck to dspi_sout invalid ?2 ns ds7 dspi_sin to dspi_sck input setup 17 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 2. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. peripheral operating requirements and behaviors kv5x data sheet, rev. 4, 06/2016 49 nxp semiconductors
ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 22. dspi classic spi timing master mode table 36. slave mode dspi timing (limited voltage range) num description min. max. unit operating voltage 2.7 3.6 v frequency of operation 15 mhz ds9 dspi_sck input cycle time 4 x t bus ns ds10 dspi_sck input high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds11 dspi_sck to dspi_sout valid 21 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2 ns ds14 dspi_sck to dspi_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 15 ns ds16 dspi_ss inactive to dspi_sout not driven 15 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 23. dspi classic spi timing slave mode peripheral operating requirements and behaviors 50 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
3.9.4 dspi switching specifications (full voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provides dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 37. master mode dspi timing (full voltage range) num description min. max. unit notes operating voltage 1.71 3.6 v 1 frequency of operation 25 mhz ds1 dspi_sck output cycle time 4 x t bus ns ds2 dspi_sck output high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds3 dspi_pcs n valid to dspi_sck delay (t bus x 2) ? 4 ns 2 ds4 dspi_sck to dspi_pcs n invalid delay (t bus x 2) ? 4 ns 3 ds5 dspi_sck to dspi_sout valid 10 ns ds6 dspi_sck to dspi_sout invalid -7.8 ns ds7 dspi_sin to dspi_sck input setup 24 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the dspi module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 3. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 24. dspi classic spi timing master mode table 38. slave mode dspi timing (full voltage range) num description min. max. unit operating voltage 1.71 3.6 v table continues on the next page... peripheral operating requirements and behaviors kv5x data sheet, rev. 4, 06/2016 51 nxp semiconductors
table 38. slave mode dspi timing (full voltage range) (continued) num description min. max. unit frequency of operation 12.5 mhz ds9 dspi_sck input cycle time 8 x t bus ns ds10 dspi_sck input high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds11 dspi_sck to dspi_sout valid 27.5 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2.5 ns ds14 dspi_sck to dspi_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 22 ns ds16 dspi_ss inactive to dspi_sout not driven 22 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 25. dspi classic spi timing slave mode 3.9.5 i 2 c see general switching specifications . 3.9.6 uart see general switching specifications . 4 dimensions dimensions 52 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
4.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to www.nxp.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 144-pin mapbga 98asa00222d 144-pin lqfp 98ass23177w 100-pin lqfp 98ass23308w pinouts and packaging 5.1 kv5x signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. 144 map bga 144 lqfp 100 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 alt8 alt9 d3 1 1 pte0 hsadc0b _ch16/ hsadc1a _ch0 hsadc0b _ch16/ hsadc1a _ch0 pte0 spi1_ pcs1 uart1_ tx xb_ out10 xb_in11 i2c1_sda trace_ clkout d2 2 2 pte1/ llwu_p0 hsadc0b _ch17/ hsadc1a _ch1 hsadc0b _ch17/ hsadc1a _ch1 pte1/ llwu_p0 spi1_ sout uart1_ rx xb_ out11 xb_in7 i2c1_scl trace_ d3 d1 3 3 pte2/ llwu_p1 hsadc0b _ch10/ hsadc1b _ch0 hsadc0b _ch10/ hsadc1b _ch0 pte2/ llwu_p1 spi1_sck uart1_ cts_b trace_ d2 e4 4 4 pte3 hsadc0b _ch11/ hsadc1b _ch1 hsadc0b _ch11/ hsadc1b _ch1 pte3 spi1_sin uart1_ rts_b trace_ d1 e5 5 vdd vdd vdd f6 6 vss vss vss e3 7 5 pte4/ llwu_p2 hsadc1a _ch4/ adc0_ hsadc1a _ch4/ adc0_ pte4/ llwu_p2 spi1_ pcs0 uart3_ tx trace_ d0 5 pinouts and packaging kv5x data sheet, rev. 4, 06/2016 53 nxp semiconductors
144 map bga 144 lqfp 100 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 alt8 alt9 se2/ adc0_ dp2 se2/ adc0_ dp2 e2 8 6 pte5 hsadc1a _ch5/ adc0_ se10/ adc0_ dm2 hsadc1a _ch5/ adc0_ se10/ adc0_ dm2 pte5 spi1_ pcs2 uart3_ rx flexpwm 1_a0 ftm3_ ch0 e1 9 7 pte6/ llwu_ p16 hsadc1b _ch7/ adc0_ se4a hsadc1b _ch7/ adc0_ se4a pte6/ llwu_ p16 spi1_ pcs3 uart3_ cts_b flexpwm 1_b0 ftm3_ ch1 f4 10 pte7 disabled pte7 uart3_ rts_b flexpwm 1_a1 ftm3_ ch2 f3 11 pte8 disabled pte8 uart5_ tx flexpwm 1_b1 ftm3_ ch3 f2 12 pte9/ llwu_ p17 disabled pte9/ llwu_ p17 uart5_ rx flexpwm 1_a2 ftm3_ ch4 f1 13 pte10/ llwu_ p18 disabled pte10/ llwu_ p18 uart5_ cts_b flexpwm 1_b2 ftm3_ ch5 g4 14 pte11 hsadc1a _ch6/ adc0_ se3/ adc0_ dp3 hsadc1a _ch6/ adc0_ se3/ adc0_ dp3 pte11 uart5_ rts_b flexpwm 1_a3 ftm3_ ch6 g3 15 pte12 hsadc1b _ch6/ adc0_ se11/ adc0_ dm3 hsadc1b _ch6/ adc0_ se11/ adc0_ dm3 pte12 flexpwm 1_b3 ftm3_ ch7 e6 16 8 vdd vdd vdd f7 17 9 vss vss vss h1 18 10 pte16 hsadc0a _ch0/ adc0_ se1/ adc0_ dp1 hsadc0a _ch0/ adc0_ se1/ adc0_ dp1 pte16 spi0_ pcs0 uart2_ tx ftm_ clkin0 ftm0_ flt3 h2 19 11 pte17/ llwu_ p19 hsadc0a _ch1/ adc0_ se9/ adc0_ dm1 hsadc0a _ch1/ adc0_ se9/ adc0_ dm1 pte17/ llwu_ p19 spi0_sck uart2_ rx ftm_ clkin1 lptmr0_ alt3 pinouts and packaging 54 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
144 map bga 144 lqfp 100 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 alt8 alt9 g1 20 12 pte18/ llwu_ p20 hsadc0b _ch0/ adc0_ se5a hsadc0b _ch0/ adc0_ se5a pte18/ llwu_ p20 spi0_ sout uart2_ cts_b i2c0_sda g2 21 13 pte19 hsadc0b _ch1/ adc0_ se6a hsadc0b _ch1/ adc0_ se6a pte19 spi0_sin uart2_ rts_b i2c0_scl cmp3_ out h3 22 vss vss vss j1 23 14 hsadc0a _ch6 hsadc0a _ch6/ adc0_ se7a hsadc0a _ch6/ adc0_ se7a j2 24 15 hsadc0a _ch7/ adc0_ se4b hsadc0a _ch7/ adc0_ se4b hsadc0a _ch7/ adc0_ se4b k1 25 16 pte20 hsadc0a _ch8/ adc0_ se5b hsadc0a _ch8/ adc0_ se5b pte20 ftm1_ ch0 uart0_ tx ftm1_ qd_pha k2 26 17 pte21 hsadc0a _ch9/ hsadc1a _ch7 hsadc0a _ch9/ hsadc1a _ch7 pte21 xb_in9 ftm1_ ch1 uart0_ rx ftm1_ qd_phb l1 27 18 hsadc0a _ch2/ hsadc1a _ch2 hsadc0a _ch2/ hsadc1a _ch2 hsadc0a _ch2/ hsadc1a _ch2 l2 28 19 hsadc0a _ch3/ hsadc1a _ch3 hsadc0a _ch3/ hsadc1a _ch3 hsadc0a _ch3/ hsadc1a _ch3 m1 29 20 hsadc0a _ch10/ hsadc1b _ch2 hsadc0a _ch10/ hsadc1b _ch2 hsadc0a _ch10/ hsadc1b _ch2 m2 30 21 hsadc0a _ch11/ hsadc1b _ch3 hsadc0a _ch11/ hsadc1b _ch3 hsadc0a _ch11/ hsadc1b _ch3 h5 31 22 vdda vdda vdda g5 32 23 vrefh vrefh vrefh g6 33 24 vrefl vrefl vrefl h6 34 25 vssa vssa vssa k3 35 adc0_ se0/ adc0_ adc0_ se0/ adc0_ adc0_ se0/ adc0_ pinouts and packaging kv5x data sheet, rev. 4, 06/2016 55 nxp semiconductors
144 map bga 144 lqfp 100 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 alt8 alt9 dp0/ cmp2_in5 dp0/ cmp2_in5 dp0/ cmp2_in5 j3 36 adc0_ se8/ adc0_ dm0/ cmp1_in2 adc0_ se8/ adc0_ dm0/ cmp1_in2 adc0_ se8/ adc0_ dm0/ cmp1_in2 m3 37 26 pte29 hsadc0a _ch4/ cmp1_ in5/ cmp0_in5 hsadc0a _ch4/ cmp1_ in5/ cmp0_in5 pte29 ftm0_ ch2 ftm_ clkin0 l3 38 27 pte30 dac0_ out/ cmp1_ in3/ hsadc0a _ch5 dac0_ out/ cmp1_ in3/ hsadc0a _ch5 pte30 ftm0_ ch3 ftm_ clkin1 l4 39 28 hsadc0a _ch12/ cmp0_ in4/ cmp2_in3 hsadc0a _ch12/ cmp0_ in4/ cmp2_in3 hsadc0a _ch12/ cmp0_ in4/ cmp2_in3 l5 40 pte13 disabled pte13 m7 41 pte22 disabled pte22 ftm2_ ch0 xb_in2 ftm2_ qd_pha m6 42 pte23 disabled pte23 ftm2_ ch1 xb_in3 ftm2_ qd_phb 29 vss vss vss l6 43 30 vdd vdd vdd 44 vss vss vss m4 45 31 pte24 hsadc0b _ch4/ hsadc1b _ch4 hsadc0b _ch4/ hsadc1b _ch4 pte24 can1_tx ftm0_ ch0 xb_in2 i2c0_scl ewm_ out_b xb_out4 uart4_ tx k5 46 32 pte25/ llwu_ p21 hsadc0b _ch5/ hsadc1b _ch5 hsadc0b _ch5/ hsadc1b _ch5 pte25/ llwu_ p21 can1_rx ftm0_ ch1 xb_in3 i2c0_sda ewm_in xb_out5 uart4_ rx k4 47 33 pte26 disabled pte26 enet_ 1588_ clkin ftm0_ ch4 uart4_ cts_b j4 48 pte27 disabled pte27 can2_tx uart4_ rts_b h4 49 pte28 disabled pte28 can2_rx j5 50 34 pta0 jtag_ tclk/ swd_clk pta0 uart0_ cts_b/ ftm0_ ch5 xb_in4 ewm_in jtag_ tclk/ swd_clk pinouts and packaging 56 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
144 map bga 144 lqfp 100 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 alt8 alt9 uart0_ col_b j6 51 35 pta1 jtag_tdi pta1 uart0_ rx ftm0_ ch6 cmp0_ out ftm2_ qd_pha ftm1_ ch1 jtag_tdi k6 52 36 pta2 jtag_ tdo/ trace_ swo pta2 uart0_ tx ftm0_ ch7 cmp1_ out ftm2_ qd_phb ftm1_ ch0 jtag_ tdo/ trace_ swo k7 53 37 pta3 jtag_ tms/ swd_dio pta3 uart0_ rts_b ftm0_ ch0 xb_in9 ewm_ out_b flexpwm 0_a0 jtag_ tms/ swd_dio l7 54 38 pta4/ llwu_p3 nmi_b pta4/ llwu_p3 ftm0_ ch1 xb_in10 ftm0_ flt3 flexpwm 0_b0 nmi_b m8 55 39 pta5 disabled pta5 ftm0_ ch2 rmii0_ rxer/ mii0_ rxer cmp2_ out jtag_ trst_b e7 56 40 vdd vdd vdd g7 57 41 vss vss vss j7 58 pta6 disabled pta6 ftm0_ ch3 clkout trace_ clkout j8 59 pta7 hsadc1b _ch8 hsadc1b _ch8 pta7 ftm0_ ch4 rmii0_ mdio/ mii0_ mdio trace_ d3 k8 60 pta8 hsadc1b _ch9 hsadc1b _ch9 pta8 ftm1_ ch0 rmii0_ mdc/ mii0_mdc trace_ d2 l8 61 pta9 disabled pta9 ftm1_ ch1 mii0_ rxd3 trace_ d1 m9 62 pta10/ llwu_ p22 disabled pta10/ llwu_ p22 ftm2_ ch0 mii0_ rxd2 ftm2_ qd_pha trace_ d0 l9 63 pta11/ llwu_ p23 disabled pta11/ llwu_ p23 ftm2_ ch1 mii0_ rxclk ftm2_ qd_phb i2c0_sda k9 64 42 pta12 cmp2_in0 cmp2_in0 pta12 can0_tx ftm1_ ch0 rmii0_ rxd1/ mii0_ rxd1 ftm1_ qd_pha i2c0_scl j9 65 43 pta13/ llwu_p4 cmp2_in1 cmp2_in1 pta13/ llwu_p4 can0_rx ftm1_ ch1 rmii0_ rxd0/ mii0_ rxd0 ftm1_ qd_phb i2c1_sda l10 66 44 pta14 cmp3_in0 cmp3_in0 pta14 spi0_ pcs0 uart0_ tx can2_tx rmii0_ crs_dv/ mii0_ rxdv i2c1_scl pinouts and packaging kv5x data sheet, rev. 4, 06/2016 57 nxp semiconductors
144 map bga 144 lqfp 100 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 alt8 alt9 l11 67 45 pta15 cmp3_in1 cmp3_in1 pta15 spi0_sck uart0_ rx can2_rx rmii0_ txen/ mii0_ txen k10 68 46 pta16 cmp3_in2 cmp3_in2 pta16 spi0_ sout uart0_ cts_b/ uart0_ col_b rmii0_ txd0/ mii0_txd0 k11 69 47 pta17 hsadc0a _ch15 hsadc0a _ch15 pta17 spi0_sin uart0_ rts_b rmii0_ txd1/ mii0_txd1 e8 70 48 vdd vdd vdd g8 71 49 vss vss vss m12 72 50 pta18 extal0 extal0 pta18 xb_in7 ftm0_ flt2 ftm_ clkin0 xb_out8 ftm3_ ch2 m11 73 51 pta19 xtal0 xtal0 pta19 xb_in8 ftm1_ flt0 ftm_ clkin1 xb_out9 lptmr0_ alt1 l12 74 52 reset_b reset_b reset_b k12 75 pta24 disabled pta24 xb_in4 mii0_txd2 fb_a29 j12 76 pta25 disabled pta25 xb_in5 mii0_ txclk fb_a28 j11 77 pta26 disabled pta26 mii0_txd3 fb_a27 j10 78 pta27 disabled pta27 mii0_crs fb_a26 h12 79 pta28 disabled pta28 mii0_ txer fb_a25 h11 80 pta29 disabled pta29 mii0_col fb_a24 h10 81 53 ptb0/ llwu_p5 hsadc0b _ch2 hsadc0b _ch2 ptb0/ llwu_p5 i2c0_scl ftm1_ ch0 ftm1_ qd_pha uart0_ rx rmii0_ mdio/ mii0_ mdio h9 82 54 ptb1 hsadc0b _ch3 hsadc0b _ch3 ptb1 i2c0_sda ftm1_ ch1 ftm0_ flt2 ewm_in ftm1_ qd_phb uart0_ tx rmii0_ mdc/ mii0_mdc g12 83 55 ptb2 hsadc0a _ch14/ cmp2_in2 hsadc0a _ch14/ cmp2_in2 ptb2 i2c0_scl uart0_ rts_b ftm0_ flt1 enet0_ 1588_ tmr0 ftm0_ flt3 g11 84 56 ptb3 hsadc0b _ch15/ cmp3_in5 hsadc0b _ch15/ cmp3_in5 ptb3 i2c0_sda uart0_ cts_b/ uart0_ col_b enet0_ 1588_ tmr1 ftm0_ flt0 g10 85 ptb4 adc0_ se6b adc0_ se6b ptb4 flexpwm 1_x0 enet0_ 1588_ tmr2 ftm1_ flt0 g9 86 ptb5 adc0_ se7b adc0_ se7b ptb5 flexpwm 1_x1 enet0_ 1588_ tmr3 ftm2_ flt0 pinouts and packaging 58 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
144 map bga 144 lqfp 100 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 alt8 alt9 f12 87 ptb6 hsadc1a _ch12 hsadc1a _ch12 ptb6 can2_tx flexpwm 1_x2 fb_ad23 f11 88 ptb7 hsadc1a _ch13 hsadc1a _ch13 ptb7 can2_rx flexpwm 1_x3 fb_ad22 f10 89 ptb8 disabled ptb8 uart3_ rts_b fb_ad21 f9 90 57 ptb9 disabled ptb9 spi1_ pcs1 uart3_ cts_b enet0_ 1588_ tmr2 fb_ad20 e12 91 58 ptb10 hsadc0b _ch6 hsadc0b _ch6 ptb10 spi1_ pcs0 uart3_ rx enet0_ 1588_ tmr3 ftm0_ flt1 fb_ad19 e11 92 59 ptb11 hsadc0b _ch7 hsadc0b _ch7 ptb11 spi1_sck uart3_ tx ftm0_ flt2 fb_ad18 h7 93 60 vss vss vss f5 94 61 vdd vdd vdd e10 95 62 ptb16 disabled ptb16 spi1_ sout uart0_ rx ftm_ clkin2 can0_tx ewm_in xb_in5 fb_ad17 e9 96 63 ptb17 disabled ptb17 spi1_sin uart0_ tx ftm_ clkin1 can0_rx ewm_ out_b fb_ad16 d12 97 64 ptb18 disabled ptb18 can0_tx ftm2_ ch0 ftm3_ ch2 flexpwm 1_a1 ftm2_ qd_pha fb_ad15 d11 98 65 ptb19 disabled ptb19 can0_rx ftm2_ ch1 ftm3_ ch3 flexpwm 1_b1 ftm2_ qd_phb fb_oe_b d10 99 66 ptb20 disabled ptb20 spi2_ pcs0 flexpwm 0_x0 cmp0_ out fb_ad31 d9 100 67 ptb21 disabled ptb21 spi2_sck flexpwm 0_x1 cmp1_ out fb_ad30 c12 101 68 ptb22 disabled ptb22 spi2_ sout flexpwm 0_x2 cmp2_ out fb_ad29 c11 102 69 ptb23 disabled ptb23 spi2_sin spi0_ pcs5 flexpwm 0_x3 cmp3_ out fb_ad28 b12 103 70 ptc0 hsadc0b _ch8 hsadc0b _ch8 ptc0 spi0_ pcs4 pdb0_ extrg ftm0_ flt1 spi0_ pcs0 fb_ad14 b11 104 71 ptc1/ llwu_p6 hsadc0b _ch9 hsadc0b _ch9 ptc1/ llwu_p6 spi0_ pcs3 uart1_ rts_b ftm0_ ch0 flexpwm 0_a3 xb_in11 fb_ad13 a12 105 72 ptc2 hsadc1b _ch10/ cmp1_in0 hsadc1b _ch10/ cmp1_in0 ptc2 spi0_ pcs2 uart1_ cts_b ftm0_ ch1 flexpwm 0_b3 xb_in6 fb_ad12 a11 106 73 ptc3/ llwu_p7 cmp1_in1 cmp1_in1 ptc3/ llwu_p7 spi0_ pcs1 uart1_ rx ftm0_ ch2 clkout ftm3_ flt0 h8 107 74 vss vss vss 108 75 vdd vdd vdd a9 109 76 ptc4/ llwu_p8 disabled ptc4/ llwu_p8 spi0_ pcs0 uart1_ tx ftm0_ ch3 cmp1_ out fb_ad11 pinouts and packaging kv5x data sheet, rev. 4, 06/2016 59 nxp semiconductors
144 map bga 144 lqfp 100 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 alt8 alt9 d8 110 77 ptc5/ llwu_p9 disabled ptc5/ llwu_p9 spi0_sck lptmr0_ alt2 xb_in2 cmp0_ out ftm0_ ch2 fb_ad10 c8 111 78 ptc6/ llwu_ p10 cmp2_ in4/ cmp0_in0 cmp2_ in4/ cmp0_in0 ptc6/ llwu_ p10 spi0_ sout pdb0_ extrg xb_in3 uart0_ rx xb_out6 i2c0_scl fb_ad9 b8 112 79 ptc7 cmp3_ in4/ cmp0_in1 cmp3_ in4/ cmp0_in1 ptc7 spi0_sin xb_in4 uart0_ tx xb_out7 i2c0_sda fb_ad8 a8 113 80 ptc8 hsadc1b _ch11/ cmp0_in2 hsadc1b _ch11/ cmp0_in2 ptc8 ftm3_ ch4 flexpwm 1_a2 fb_ad7 d7 114 81 ptc9 hsadc1b _ch12/ cmp0_in3 hsadc1b _ch12/ cmp0_in3 ptc9 ftm3_ ch5 flexpwm 1_b2 fb_ad6 c7 115 82 ptc10 hsadc1b _ch13 hsadc1b _ch13 ptc10 i2c1_scl ftm3_ ch6 flexpwm 1_a3 fb_ad5 b7 116 83 ptc11/ llwu_ p11 hsadc1b _ch14 hsadc1b _ch14 ptc11/ llwu_ p11 i2c1_sda ftm3_ ch7 flexpwm 1_b3 fb_rw_b a7 117 84 ptc12 disabled ptc12 can2_tx ftm_ clkin0 flexpwm 1_a1 ftm3_ flt0 spi2_ pcs1 fb_ad27 uart4_ rts_b d6 118 85 ptc13 disabled ptc13 can2_rx ftm_ clkin1 flexpwm 1_b1 fb_ad26 uart4_ cts_b c6 119 86 ptc14 disabled ptc14 i2c1_scl i2c0_scl flexpwm 1_a0 fb_ad25 uart4_ rx b6 120 87 ptc15 disabled ptc15 i2c1_sda i2c0_sda flexpwm 1_b0 fb_ad24 uart4_ tx 121 88 vss vss vss 122 89 vdd vdd vdd a6 123 90 ptc16 disabled ptc16 can1_rx uart3_ rx enet0_ 1588_ tmr0 flexpwm 1_a2 fb_cs5_ b/ fb_tsiz1/ fb_be23_ 16_b d5 124 91 ptc17 disabled ptc17 can1_tx uart3_ tx enet0_ 1588_ tmr1 flexpwm 1_b2 fb_cs4_ b/ fb_tsiz0/ fb_be31_ 24_b c5 125 92 ptc18 disabled ptc18 uart3_ rts_b enet0_ 1588_ tmr2 flexpwm 1_a3 fb_tbst_ b/ fb_cs2_ b/ fb_be15_ 8_b b5 126 ptc19 disabled ptc19 uart3_ cts_b enet0_ 1588_ tmr3 flexpwm 1_b3 fb_cs3_ b/ fb_ta_b pinouts and packaging 60 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
144 map bga 144 lqfp 100 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 alt8 alt9 fb_be7_ 0_b a5 127 93 ptd0/ llwu_ p12 disabled ptd0/ llwu_ p12 spi0_ pcs0 uart2_ rts_b ftm3_ ch0 ftm0_ ch0 flexpwm 0_a0 fb_ale/ fb_cs1_ b/ fb_ts_b flexpwm 1_a0 d4 128 94 ptd1 hsadc1a _ch11 hsadc1a _ch11 ptd1 spi0_sck uart2_ cts_b ftm3_ ch1 ftm0_ ch1 flexpwm 0_b0 fb_cs0_b flexpwm 1_b0 c4 129 95 ptd2/ llwu_ p13 disabled ptd2/ llwu_ p13 spi0_ sout uart2_ rx ftm3_ ch2 ftm0_ ch2 flexpwm 0_a1 i2c0_scl fb_ad4 flexpwm 1_a1 b4 130 96 ptd3 disabled ptd3 spi0_sin uart2_ tx ftm3_ ch3 ftm0_ ch3 flexpwm 0_b1 i2c0_sda fb_ad3 flexpwm 1_b1 a4 131 97 ptd4/ llwu_ p14 disabled ptd4/ llwu_ p14 spi0_ pcs1 uart0_ rts_b ftm0_ ch4 flexpwm 0_a2 ewm_in spi1_ pcs0 fb_ad2 a3 132 98 ptd5 hsadc1a _ch8 hsadc1a _ch8 ptd5 spi0_ pcs2 uart0_ cts_b/ uart0_ col_b ftm0_ ch5 flexpwm 0_b2 ewm_ out_b spi1_sck fb_ad1 a2 133 99 ptd6/ llwu_ p15 hsadc1a _ch9 hsadc1a _ch9 ptd6/ llwu_ p15 spi0_ pcs3 uart0_ rx ftm0_ ch6 ftm1_ ch0 ftm0_ flt0 spi1_ sout fb_ad0 m10 134 vss vss vss f8 135 vdd vdd vdd a1 136 100 ptd7 disabled ptd7 uart0_ tx ftm0_ ch7 ftm1_ ch1 ftm0_ flt1 spi1_sin c9 137 ptd8/ llwu_ p24 disabled ptd8/ llwu_ p24 i2c1_scl uart5_ rx flexpwm 0_a3 fb_a16 b9 138 ptd9 disabled ptd9 i2c1_sda uart5_ tx flexpwm 0_b3 fb_a17 b3 139 ptd10 disabled ptd10 uart5_ rts_b flexpwm 0_a2 fb_a18 b2 140 ptd11/ llwu_ p25 disabled ptd11/ llwu_ p25 spi2_ pcs0 uart5_ cts_b flexpwm 0_b2 fb_a19 b1 141 ptd12 disabled ptd12 spi2_sck ftm3_ flt0 xb_in5 xb_out5 flexpwm 0_a1 fb_a20 c3 142 ptd13 disabled ptd13 spi2_ sout xb_in7 xb_out7 flexpwm 0_b1 fb_a21 c2 143 ptd14 disabled ptd14 spi2_sin xb_in11 xb_ out11 flexpwm 0_a0 fb_a22 c1 144 ptd15 disabled ptd15 spi2_ pcs1 flexpwm 0_b0 fb_a23 pinouts and packaging kv5x data sheet, rev. 4, 06/2016 61 nxp semiconductors
5.2 kv5x pinouts the below figure shows the pinout diagram for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see the previous section. 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 a b c d e f g h j a b c d e f g h j 10 k k 10 11 11 l l 12 12 m m pta18 ptc8 ptc4/ llwu_p8 ptc3/ llwu_p7 ptc2 pta1 pta6pta0pte27 adc0_se8/ adc0_dm0/ cmp1_in2 adc0_se0/ adc0_dp0/ cmp2_in5 pte26 pte25/ llwu_p21 pta2 pta3 pta8 pta7 vssvssvssavddapte28vss pte17/ llwu_p19 hsadc0a_ ch7/ adc0_se4b pte21 hsadc0a_ ch3/ hsadc1a_ ch3 pte30 hsadc0a_ ch12/ cmp0_in4/ cmp2_in3 pte13 vdd pta4/ llwu_p3 pta9 pta11/ llwu_p23 pta12 pta13/ llwu_p4 ptb1 pta27 ptb0/ llwu_p5 ptb4ptb5vssvssvreflvrefhpte11pte12pte19 pte18/ llwu_p20 pte16 hsadc0a_ ch6 pte20 hsadc0a_ ch2/ hsadc1a_ ch2 hsadc0a_ ch10/ hsadc1b_ ch2 hsadc0a_ ch11/ hsadc1b_ ch3 pte29 pte24 pte23 pte22 pta5 pta10/ llwu_p22 vss pta16 pta14 ptb3 pta29 pta26 pta17 pta15 pta19 reset_b pta24 pta25 pta28 ptb2 ptb6ptb7ptb8ptb9vdd vdd ptb17 ptb16 ptb10ptb11 ptb19 ptb18 ptb22ptb23 ptb20ptb21 ptc5/ llwu_p9 ptd8/ llwu_p24 ptc6/ llwu_p10 ptc7 ptd9 ptc1/ llwu_p6 ptc0 vss vss vddvdd ptc13 ptc9 ptc11/ llwu_p11 ptc10 ptc19 ptc15 ptc14ptc18 ptd2/ llwu_p13 ptd3ptd10 ptd13 pte0 ptd1 ptc17 vdd vddpte7 pte3 pte4/ llwu_p2 pte8 pte9/ llwu_p17 pte10/ llwu_p18 pte6/ llwu_p16 pte5 pte1/ llwu_p0 pte2/ llwu_p1 ptd15 ptd14 ptd11/ llwu_p25 ptd12 ptc12ptc16 ptd0/ llwu_p12 ptd4/ llwu_p14 ptd5 ptd6/ llwu_p15 ptd7 figure 26. 144 mapbga pinout diagram pinouts and packaging 62 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 75 74 73 60 59 58 57 56 55 54 53 52 51 72 71 70 69 68 67 66 65 64 63 62 61 25 24 23 22 21 40 39 38 37 50 49 48 47 46 45 44 43 42 41 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 98 97 96 95 94 93 92 91 90 89 88 80 81 82 83 84 85 86 87 100 108 vdd 107 106 105 104 103 102 101 vss ptc3/llwu_p7 ptc2 ptc1/llwu_p6 ptc0 ptb23 ptb22 116 ptc11/llwu_p11 115 114 113 112 111 110 109 ptc10 ptc9 ptc8 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 124 ptc17 123 122 121 120 119 118 117 ptc16 vdd vss ptc15 ptc14 ptc13 ptc12 132 ptd5 131 130 129 128 127 126 125 ptd4/llwu_p14 ptd3 ptd2/llwu_p13 ptd1 ptd0/llwu_p12 ptc19 ptc18 140 ptd11/llwu_p25 139 138 137 136 135 134 133 ptd10 ptd9 ptd8/llwu_p24 ptd7 vdd vss ptd6/llwu_p15 144 143 142 141 ptd15 ptd14 ptd13 ptd12 ptb20 pta28 pta27 pta26 pta25 ptb19 ptb18 ptb17 ptb16 vdd vss ptb11 ptb10 ptb9 ptb8 ptb7 pta29 ptb0/llwu_p5 ptb1 ptb2 ptb3 ptb4 ptb5 ptb6 ptb21 pta24 reset_b pta19 pta18 vss vdd pta17 pta16 pta15 pta14 pta13/llwu_p4 pta12 pta11/llwu_p23 pta10/llwu_p22 pta9 pta8 pta7 pta6 vss vdd pta5 pta4/llwu_p3 pta3 pta2 pta1 pta0 pte28 pte27 pte26 pte25/llwu_p21 pte24 vss vdd pte23 pte22 pte13 hsadc0a_ch12/cmp0_in4/cmp2_in3 pte30 pte29 pte18/llwu_p20 pte17/llwu_p19 pte16 vss vdd pte12 pte11 pte10/llwu_p18 pte9/llwu_p17 pte8 pte7 pte6/llwu_p16 pte5 pte4/llwu_p2 vss vdd pte3 pte2/llwu_p1 pte1/llwu_p0 pte0 pte20 hsadc0a_ch7/adc0_se4b hsadc0a_ch6 vss pte19 adc0_se8/adc0_dm0/cmp1_in2 adc0_se0/adc0_dp0/cmp2_in5 vssa vrefl vrefh vdda hsadc0a_ch11/hsadc1b_ch3 hsadc0a_ch10/hsadc1b_ch2 hsadc0a_ch3/hsadc1a_ch3 hsadc0a_ch2/hsadc1a_ch2 pte21 figure 27. 144 lqfp pinout diagram pinouts and packaging kv5x data sheet, rev. 4, 06/2016 63 nxp semiconductors
60 59 58 57 56 55 54 53 52 51 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 hsadc0a_ch10/hsadc1b_ch2 hsadc0a_ch3/hsadc1a_ch3 hsadc0a_ch2/hsadc1a_ch2 pte21 pte20 hsadc0a_ch7/adc0_se4b hsadc0a_ch6 pte19 pte18/llwu_p20 pte17/llwu_p19 pte16 vss vdd pte6/llwu_p16 pte5 pte4/llwu_p2 pte3 pte2/llwu_p1 pte1/llwu_p0 pte0 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 vdd vss ptc3/llwu_p7 ptc2 ptc1/llwu_p6 ptc0 ptb23 ptb22 ptb21 ptb20 ptb19 ptb18 ptb17 ptb16 vdd vss ptb11 ptb10 ptb9 ptb3 ptb2 ptb1 ptb0/llwu_p5 reset_b pta19 25 24 23 22 21 vssa vrefl vrefh vdda hsadc0a_ch11/hsadc1b_ch3 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 ptd6/llwu_p15 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 50 49 48 47 46 45 44 43 42 41 pta18 vss vdd pta17 pta16 pta15 pta14 pta13/llwu_p4 pta12 vss vdd pta5 pta4/llwu_p3 pta3 pta2 pta1 pta0 pte26 pte25/llwu_p21 pte24 vdd vss hsadc0a_ch12/cmp0_in4/cmp2_in3 pte30 pte29 98 ptd5 97 ptd4/llwu_p14 96 ptd3 95 ptd2/llwu_p13 94 ptd1 93 ptd0/llwu_p12 92 ptc18 91 ptc17 90 ptc16 89 vdd 88 vss 80 ptc8 ptc9 ptc10 81 82 83 ptc11/llwu_p11 84 ptc12 85 ptc13 86 ptc14 87 ptc15 100 ptd7 figure 28. 100 lqfp pinout diagram 6 ordering parts ordering parts 64 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
6.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to www.nxp.com and perform a part number search for the mkv5x device numbers. 7 part identification 7.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 7.2 format part numbers for this device have the following format: q kv## a fff t pp cc n 7.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status ? m = fully qualified, general market flow ? p = prequalification kv## kinetis family ? kv58 ? kv56 a key attribute ? f = cortex-m7 fff program flash memory size ? 1m0 = 1 mb ? 512 = 512 kb t temperature range (c) ? v = C40 to 105 pp package identifier ? lq = 144 lqfp (20 mm x 20 mm) ? ll = 100 lqfp (14 mm x 14 mm) ? md = 144 mapbga (13 mm x 13 mm) cc maximum cpu frequency (mhz) ? 24 = 240 mhz n packaging type ? r = tape and reel ? (blank) = trays part identification kv5x data sheet, rev. 4, 06/2016 65 nxp semiconductors
7.4 example this is an example part number: mkv58f1m0vlq24 mkv56f512vll24 8 terminology and guidelines 8.1 definition: operating requirement an operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 8.1.1 example this is an example of an operating requirement: symbol description min. max. unit v dd 1.0 v core supply voltage 0.9 1.1 v 8.2 definition: operating behavior unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 8.2.1 example this is an example of an operating behavior: terminology and guidelines 66 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
symbol description min. max. unit i wp digital i/o weak pullup/ pulldown current 10 130 a 8.3 definition: attribute an attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 8.3.1 example this is an example of an attribute: symbol description min. max. unit cin_d input capacitance: digital pins 7 pf 8.4 definition: rating a rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: ? operating ratings apply during operation of the chip. ? handling ratings apply when the chip is not powered. 8.4.1 example this is an example of an operating rating: symbol description min. max. unit v dd 1.0 v core supply voltage C0.3 1.2 v terminology and guidelines kv5x data sheet, rev. 4, 06/2016 67 nxp semiconductors
8.5 result of exceeding a rating 40 30 20 10 0 measured characteristic operating rating failures in time (ppm) the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 8.6 relationship between ratings and operating requirements C - no permanent failure - correct operation normal operating range fatal range expected permanent failure fatal range expected permanent failure operating rating (max.) operating requirement (max.) operating requirement (min.) operating rating (min.) operating (power on) degraded operating range degraded operating range C no permanent failure handling range fatal range expected permanent failure fatal range expected permanent failure handling rating (max.) handling rating (min.) handling (power off) - no permanent failure - possible decreased life - possible incorrect operation - no permanent failure - possible decreased life - possible incorrect operation 8.7 guidelines for ratings and operating requirements follow these guidelines for ratings and operating requirements: ? never exceed any of the chips ratings. ? during normal operation, dont exceed any of the chips operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. terminology and guidelines 68 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
8.8 definition: typical value a typical value is a specified value for a technical characteristic that: ? lies within the range of values specified by the operating behavior ? given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions typical values are provided as design guidelines and are neither tested nor guaranteed. 8.8.1 example 1 this is an example of an operating behavior that includes a typical value: symbol description min. typ. max. unit i wp digital i/o weak pullup/pulldown current 10 70 130 a 8.8.2 example 2 this is an example of a chart that shows typical values for various voltage and temperature conditions: terminology and guidelines kv5x data sheet, rev. 4, 06/2016 69 nxp semiconductors
0.90 0.95 1.00 1.05 1.10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 c 105 c 25 c C40 c v dd (v) i (a) dd_stop t j 8.9 typical value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 c v dd 3.3 v supply voltage 3.3 v 9 revision history the following table provides a revision history for this document. table 39. revision history rev. no. date substantial changes 0 02/2015 initial release 1 06/2015 ? updated the features list to include flexbus, trng, mmcau, advanced watchdog timer and jtag modules ? updated the ordering information table to highlight differences in the parts in terms of flash, sram, modules or instances. table continues on the next page... revision history 70 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
table 39. revision history (continued) rev. no. date substantial changes ? added kv5x block diagram ? editorial changes in the table "recommended operating conditions." ? removed the typical values column from the table "recommended operating conditions." ? removed the following parameters from the table "recommended operating conditions." ? output source current high (i oh ) ? output source current low (i ol ) ? oscillator input voltage high(v ihosc ) ? oscillator input voltage low (v ilosc ) ? dac output current drive strength (c out ) ? added hvd characteristics to the table "lvd, and por operating requirements" and changed the title to hvd, lvd, and por operating requirements." ? added the following parameters to the table "voltage and current operating behaviors" ? output high current total for all ports (i oht ) ? output low current total for all ports (i ohl) ? internal pull-down resistance (r pd ) ? removed the footnote "ptc6 and ptc7 are true open drain so have no high drive output transistor so there is no voh spec for them. these pins must be terminated with a pull-up resistor to vdd" from the table "voltage and current operating behaviors" ? added a note above the table "low power mode peripheral adders typical value" suggesting that the values are preliminary data. ? updated the notes in the table "power consumption operating behaviors" for run mode currents with all peripherals disabled. ? updated the table "emc radiated emissions operating behaviors" by splitting description column into conditions and clocks columns. ? changed typ. values to tbds in the table "emc radiated emissions operating behaviors." ? updated the table "typical device clock specifications" ? added a footnote to the ambient temperature entry in the table "thermal operating requirements" ? updated the table "thermal attributes" ? changed adc to hsadc in the title of the section "12-bit sar high speed analog-to- digital converter (adc) parameters" ? changed minimum operating voltage value from 2.7 v to 1.71 v in the table "mii signal switching specifications" and rmii signal switching specifications." 2 10/2015 ? updated the part numbers in the table orderable part numbers summary and the front page ? in the features list: ? updated the instances of uart and spi modules ? added ether module to the list of communication interfaces ? remove micro trace buffer from the list of system peripherals ? in table operating requirements , removed rows for n f , t r , and t flret ? in table port voltage and current operating behaviors , added i icio , i iccont , and v odpu rows ? updated table power mode transition operating behaviors ? updated table power consumption operating behaviors ? updated table emc radiated emissions operating behaviors ? updated table general switching specifications ? in section dspi switching specifications (limited voltage range) ? removed the notes ? removed table "master mode dspi timing for fast pads (limited voltage range)" table continues on the next page... revision history kv5x data sheet, rev. 4, 06/2016 71 nxp semiconductors
table 39. revision history (continued) rev. no. date substantial changes ? removed the tbale "master mode dspi timing for open drain pads (limited voltage range)" ? removed the table "slave mode dspi timing for fast pads (limited voltage range)" ? removed the table "slave mode dspi timing for open drain pads (limited voltage range)" ? removed the table "master mode dspi timing fast pads (full voltage range)" ? removed the table "master mode dspi timing open drain pads (full voltage range)" ? removed the table "slave mode dspi timing for fast pads (full voltage range)" ? removed the table "slave mode dspi timing for open drain pads (full voltage range)" ? updated the pinouts ? updated table device clock specifications 3 02/2016 ? added new part numbers for 240 mhz and removed the 220 mhz and 200 mhz part numbers ? updated the document number to reflect change from 220 mhz to 240 mhz ? updated voltage and current operating ratings ? updated operating requirements ? updated vlps run and stop run values in power mode transition operating behaviors ? in section power consumption operating behaviors : ? added a note at the beginning of the table ? updated table to reflect 240 mhz values ? updated typical device clock specifications ? in section mcg specifications , updated the values listed under "pll" 4 06/2016 ? updated pwm resolution in the introduction to 260 ps ? added table enhanced nanoedge pwm characteristics revision history 72 kv5x data sheet, rev. 4, 06/2016 nxp semiconductors
how to reach us: home page: nxp.com web support: nxp.com/support information in this document is provided solely to enable system and software implementers to use nxp products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. nxp reserves the right to make changes without further notice to any products herein. nxp makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does nxp assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters that may be provided in nxp data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including typicals, must be validated for each customer application by customer's technical experts. nxp does not convey any license under its patent rights nor the rights of others. nxp sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/salestermsandconditions . nxp, the nxp logo, nxp secure connections for a smarter world, freescale, the freescale logo, and kinetis are trademarks of nxp b.v. all other product or service names are the property of their respective owners. arm, the arm powered logo, and cortex are registered trademarks of arm limited (or its subsidiaries) in the eu and/or elsewhere. all rights reserved. ?2016 nxp b.v. document number kv5xp144m240 revision 4, 06/2016

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